Identification of crosstalk switch failures in domino CMOS circuits

Capacitative coupling will become a dominant problem due to increased parasitic capacitance between adjacent wires and faster signal switching rates. The coupling problem is more acute for domino logic circuits since an irreversible gate output transition can result. We present a method to analyze domino circuits for susceptibility to crosstalk failures from a layout-extracted netlist. Specifically, sites in the circuit that may fail due to crosstalk are identiJed. In addition, failure sites are partitioned into two categories (faults o r design errors) based on their likelihood of occurrence in the context of manufacturing variations. The method has been implemented and applied to a dual-rail domino Wallace tree circuit with little loss in accuracy, resulting in a 37X speedup over a full analysis using Hspice.